Although among the non-volatile memory devices such as MNOS memories there have been memories having a memory holding capability of more than ten years, for obtaining a more reliable memory holding capability, it is common to employ a so-called refreshing operation, that is, the repeated operation, over an adequate interval, of reading-out of the contents in an address of the memory and rewriting-in of the same memory contents into the same address. In this refreshing operation of the memory, there has been a problem in that the refreshing action takes a rather long time. For example, in a MNOS memory, about 150 msec is necessary for its read-out and write-in action, respectively, per address, that is, about 300 msec or more is necessary for completion of a total refreshing action per address. In such a rather slow refreshing action, there is always a risk with a high probability that the power supply will shut off during the course of the refreshing action due to turning-off of the power switch or the stoppage of the power supply. In such a case false operations such as a permanent loss of the memory or an accidental conversion of the memory contents might be caused.
Taking an example of the conventional refreshing scheme, the abovementioned problem in a conventional scheme is explained below. In a MNOS memory, a data signal at an address to be refreshed (hereinafter this address is called as a refreshing address) is read out from the addressed location and is stored first in a data register comprising, for example, a shift register. Then as a next step all of the contents of this refreshing address is erased and thereafter the data signal, which has been stored in the data register, is rewritten into this refreshing address. In the above process, since the data register used is a volatile memory, if the power supply is shut off during the processes after the erasure process but before the rewriting process, the contents of the data register are all erased. Accordingly, the entire data signal of the refreshing address is lost forever or is lost partly, giving falsely converted data.
For preventing the problem described above, in the conventional refreshing scheme of a MNOS memory, it is constructed in a manner such that, even when the power supply is shut off during the course of the refreshing action, the power supply inside the device is kept running for a period which is enough to cover the necessary time for finishing the refreshing routine presently in progress, thereby the memory is protected from the aforementioned problem. However, for attaining the abovementioned countermeasure for the false operations in the MNOS memory, any means capable of holding the power supply inside the device for at least 300 msec is necessary. This means an installation of a bulky capacitor. Even with the use of an electrolytic capacitor, the device becomes insufficiently compact, and also the construction of its control circuit becomes complicated causing the cost of the device to rise. These drawbacks have been existing in the conventional refreshing schemes employed in non-volatile memories such as in MNOS memories.